In the manufacture of micro-scale or nano-scale devices, various fabrication processes are executed and repeatedly performed to create functional device elements on a substrate. Examples of micro-scale or nano-scale devices include semiconductor devices, electronic devices, mechanical devices, etc. Examples of fabrication processing include processes for film-forming, etching, patterning, cleaning, doping, annealing, treating, planarizing, etc.
Typically, these devices are produced as part of a layered device fabrication process of, for example, a substrate (e.g., a semiconductor wafer). In some instances, a coating is “spun-on” to the substrate to form a uniform layer or film. Spin coating a material enhances its uniformity in coverage and planarization. As used herein, planarization or planar refers to the consistent flatness of a layer or film.
Spin coating (or spin-on coating) is a procedure used to deposit uniform thin films to flat substrates (e.g., semiconductor wafer). Usually, a small amount of coating material is applied on the center of the substrate, which is either spinning at low speed or not spinning at all. The substrate is then rotated at high speed in order to spread the coating material by centrifugal force. A machine used for spin coating is called a spin coater, or simply spinner.
Rotation is continued while the fluid spins off the edges of the substrate, until the desired thickness of the film is achieved. The applied solvent is usually volatile, and simultaneously evaporates. So, the higher the angular speed of spinning, the thinner the film. The thickness of the film also depends on the material properties, such as the viscosity and concentration of the solution and the solvent.
Traditionally, the micro- and nano-fabrication of semiconductor transistors are formed in-plane—thus are often referred to two-dimensional (2D) or planar devices. When formed, the semiconductor transistors are interconnected via metallization/wiring layers formed in overlying layers of circuitry. While scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, the scaling efforts introduce new and greater challenges as scaling enters single digit nanometer-scale device features.
In addition, device fabricators have expressed a desire for out-of-plane, or three-dimensional (3D), non-planar devices. The decreasing scales for fabrication coupled with the ascension of device features into the third dimension have led to increasingly complex topography. Thus, it is more difficult than ever to achieve planarization.